In order to reduce leakage current due to decreased thickness of a gate dielectric layer, a layer having a high-k dielectric constant may be used. Accordingly, a hafnium-based insulating layer, such as a hafnium oxide layer or a hafnium silicon oxide layer, can be used. However, if a hafnium-based insulating layer is used with a polysilicon gate electrode, the bonding between the hafnium-based oxide layer and the polysilicon layer can be inadequate so that a Fermi level pinning phenomenon can affect the work function of the gate electrode, which can lead to an increase in the threshold voltage Vth of the device. Moreover, the increase of the threshold voltage in a P-type metal oxide semiconductor (PMOS) transistor region may become significantly more than the threshold voltage of an N-type metal oxide semiconductor (NMOS) transistor in the same device.
A method of fabricating an integrated circuit having a dual-gate structure is discussed in U.S. Pat. No. 5,567,642 ('642) entitled Method of fabricating gate electrode of CMOS device. According to the '642 patent, a gate electrode including a polysilicon layer and a silicide pattern is disposed in the PMOS transistor region, whereas and a gate electrode of an NMOS transistor (in the NMOS region) is polysilicon.